While 3D NAND revolutionalized storage, using height to stack multiple NAND flash cells in layers with a much smaller footprint and lowered costs significantly, SK Hynix is trying to go for 4, this is a bit far removed from reality as it implies a 4th dimension being added somehow though, in reality, it is probably more similar to technology shown before by Micron and Intel in the past.
SK Hynix Shows New “4D NAND” At Flash Memory Summit
The design by SK Hynix uses a charge trap design similar to flash produced by Samsung and Western Digital and Toshiba’s partnership. While SK Hynix has used Charge Trap Flash (CTF) designs for several years, meaning this really isn’t anything very new, and currently Micron and Intel are the only two companies that are using floating gate technology.
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In the long term Intel and Micron plan to split ways on their partnership in flash development after the next generation flash comes to retail shelves, at which point Micron will use their own Replacement Gate technology which is a re-brand of Charge Trap Flash design, meaning in the next year or so Intel will be the last holdout on floating gate technology.
With that little bit of the current state of flash memory aside, let’s talk about SK Hynix’s 4D NAND compared to other 3D NAND products, well the company says its CTF design paired with the Periphery Under Cell (PUC) technology. Basically, 3D flash is made up of two primary parts: the array and its periphery circuitry that lines the edges of the die. The circuitry controls the array while consuming die space and increases its complexity and size as more NAND layers are added. this added complexity and size increases the cost of the product itself.
SK Hynix’s way of dealing with this problem is the 4D NAND uses the same PUC design which places the circuitry under the array instead of around it. This should increase density and reduces costs. Though this design has been seen before with Intel and Micron on their very first implementation of 3D flash though they themselves referred to it as “CMOS under Array” (CuA). Samsung has also pointed out that they will be using a similar design in the future, so this isn’t anything truely groundbreaking, unfortunately.
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That being said the road map seems quite impressive marketing talk aside as the images above will tell the story here.
Source: Toms Hardware
